An embodiment relates to a silicon single crystal wafer.
An embodiment relates to a method of manufacturing a silicon single crystal wafer.
An embodiment relates to a method of detecting defects in a silicon single crystal wafer.
A silicon single crystal wafer is widely used for a semiconductor device that needs to be large scale integrated.
In order to increase a yield of such a semiconductor device, the silicon single crystal wafer needs to have an excellent membrane quality.
The silicon single crystal wafer is one of a plurality of sheets that is obtained by cutting silicon ingot after the silicon ingot grows by typically using a Czochralski crystal-growing methodology (hereinafter, referred to as a CZ method)
The silicon ingot grows by controlling the relation between a pulling speed V and a temperature gradient G. The pulling speed indicates a speed at which the silicon ingot grows. The temperature gradient G indicates a temperature near a solid-liquid interface of the crystal.
In order to obtain a lot of semiconductor devices, the diameter of the silicon single crystal wafer needs to be large and to this end, the diameter of the silicon ingot needs to be large.
However, as the diameter of the silicon ingot becomes large, it becomes difficult to control the pulling speed V/temperature gradient G. Thus, the silicon ingot has various defects, such as FPD, LSTD, COP, etc. and due to such defects, the yield of the semiconductor device may become worse.
Prior to describing such defects, factors will be described which respectively determine inclusion concentrations of a vacancy-point defect that is called vacancy (hereinafter, referred to as V) included on the silicon single crystal wafer, and an interstitial silicon point defect that is called interstitial (hereinafter, referred to as I).
For the silicon single crystal wafer, a V-rich region indicates a vacancy condensed defective region that occurs due to a lack of a silicon atom. An I-rich region indicates an interstitial-silicon condensed defective region due to an extra silicon atom.
There is a neutral region, for example, an N region, between the V-rich region and the I-rich region. The N region has no lack, no extra, little lack, or little extra in atom.
The above-mentioned defects such as FPD, LSTD, COP, etc. occur when vacancy V silicon or interstitial I silicon is supersaturated, and even if there is rather atom deviation, such defects do not occur below super-saturation.
The concentration of the point defect by the vacancy V silicon and that of the point defect by the interstitial I silicon are determined by the relation between the pulling speed V and the temperature gradient G. A defect called an oxidation induced stacking fault (OSF) is distributed near the boundary between the V-rich region and the I-rich region in a ring shape (hereinafter, referred to an OSF ring) when viewed from the vertical section with respect to the growing axis of a crystal. A defect resulting from the growth of the crystal is already described in detail in Japanese Patent Laid-Open No. 2002-211093, for example.
According to the Japanese Patent Laid-Open No. 2002-211093, the N region is re-classified into an Nv region where the vacancy V silicon is predominant, and an Ni region where the interstitial I silicon is predominant.
When heat treatment is performed in the Nv region, oxygen precipitates (hereinafter, referred to as a bulk micro defect (BMD)) are represented, but in the Ni region, the oxygen precipitates are rarely represented. In this case, even if heat treatment is performed in the Ni region, the oxygen precipitates are rarely represented and in other words, the density of the BMD is low as well as there is a limitation in that it is not easy to getter pollution if the pollution occurs in device processes.